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LTC1606 16-Bit, 250ksps, Single Supply ADC
FEATURES
s s s s s s s s s s s s
DESCRIPTIO
Sample Rate: 250ksps Single 5V Supply Bipolar Input Range: 10V Signal-to-Noise Ratio: 90dB Typ Power Dissipation: 75mW Typ Guaranteed No Missing Codes Integral Nonlinearity: 2.0LSB Max Operates with Internal or External Reference Internal Synchronized Clock 28-Pin SSOP and SO Packages 100ksps Version (LTC1605) Improved 2nd Source to AD976A and ADS7805
The LTC (R)1606 is a 250ksps, sampling 16-bit A/D converter that draws only 75mW (typical) from a single 5V supply. This easy-to-use device includes sample-andhold, precision reference, switched capacitor successive approximation A/D and trimmed internal clock. The LTC1606's input range is an industry standard 10V. Maximum DC specs include 2.0LSB INL and 16 bits no missing codes over temperature. An external reference can be used if greater accuracy over temperature is needed. The 90dB signal-to-noise ratio offers an improvement of 3dB over competing devices, and the RMS transition noise is reduced (0.65LSB vs 1LSB) relative to competitive parts. The ADC has a microprocessor compatible, 16-bit or two byte parallel output port. A convert start input and a data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s
Industrial Process Control Multiplexed Data Acquisition Systems High Speed Data Acquisition for PCs Digital Signal Processing
BASIC CO FIGURATIO
5V
Low Power, 250kHz, 16-Bit Sampling ADC on 5V Supply
10F 28 LTC1606 27 VDIG VANA 7.35k 6 TO 13 15 TO 22 16-BIT SAMPLING ADC 9k BUSY 26 1.64x BUFFER 3 REF 4k REFERENCE AGND1 2 AGND2 5 DGND 14
1606 TA01
0.1F
2.0 1.5
10V 200 INPUT 33.2k
1 VIN
D15 TO D0
2.5k 4 CAP
INL (LSB)
16-BIT OR 2 BYTE PARALLEL BUS
4.096V 10F
2.5V 2.2F
CONTROL LOGIC AND TIMING
CS 25 R/C 24 BYTE 23
DIGITAL CONTROL SIGNALS
U
Typical INL Curve
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 16384 32768 CODE
1606 G04
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49152
65535
1
LTC1606
ABSOLUTE
(Notes 1, 2)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW VIN 1 AGND1 2 REF 3 CAP 4 AGND2 5 D15 (MSB) 6 D14 7 D13 8 D12 9 D11 10 D10 11 D9 12 D8 13 DGND 14 G PACKAGE 28-LEAD PLASTIC SSOP 28 VDIG 27 VANA 26 BUSY 25 CS 24 R/C 23 BYTE 22 D0 21 D1 20 D2 19 D3 18 D4 17 D5 16 D6 15 D7 SW PACKAGE 28-LEAD PLASTIC SO
VANA .......................................................................... 7V VDIG to VANA ........................................................... 0.3V VDIG ........................................................................... 7V Ground Voltage Difference DGND, AGND1 and AGND2 .............................. 0.3V Analog Inputs (Note 3) VIN ..................................................................... 25V CAP ............................ VANA + 0.3V to AGND2 - 0.3V REF .................................... Indefinite Short to AGND2 Momentary Short to VANA Digital Input Voltage (Note 4) ........ VDGND - 0.3V to 10V Digital Output Voltage ........ VDGND - 0.3V to VDIG + 0.3V Power Dissipation .............................................. 500mW Operating Ambient Temperature Range LTC1606AC/LTC1606C ............................ 0C to 70C LTC1606AI/LTC1606I ......................... - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1606ACG LTC1606AIG LTC1606CG LTC1606IG LTC1606ACSW LTC1606AISW LTC1606CSW LTC1606ISW
TJMAX = 125C, JA = 95C/W (G) TJMAX = 125C, JA = 130C/W (SW)
Consult factory for parts specified with wider operating temperature ranges.
CO VERTER CHARACTERISTICS
PARAMETER Resolution No Missing Codes Transition Noise Integral Linearity Error Bipolar Zero Error Bipolar Zero Error Drift Full-Scale Error Drift Full-Scale Error Full-Scale Error Drift Power Supply Sensitivity VANA = VDIG = VDD (Note 7) Ext. Reference = 2.5V (Note 8) CONDITIONS
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 5, 6)
MIN
q q
LTC1606 TYP
MAX
MIN 16 16
LTC1606A TYP
MAX
UNITS Bits Bits
16 15 0.65 3 10 2 7
0.65 2 10 2 5 0.50 0.25 2 8 8
LSBRMS LSB mV ppm/C ppm/C % ppm/C LSB
q q
Ext. Reference = 2.5V (Notes 12, 13) Ext. Reference = 2.5V VDD = 5V 5% (Note 9)
q
2
2
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W
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WW
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LTC1606
A ALOG I PUT
SYMBOL VIN CIN RIN PARAMETER Analog Input Range (Note 9) Analog Input Capacitance Analog Input Impedance
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS 4.75V VANA 5.25V, 4.75V VDIG 5.25V
q
DY A IC ACCURACY
SYMBOL S/(N + D) PARAMETER
Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal (Note 14) 10kHz Input Signal 20kHz, - 60dB Input Signal Total Harmonic Distortion Peak Harmonic or Spurious Noise Full-Power Bandwidth Aperture Delay Aperture Jitter Transient Response Overvoltage Recovery Full-Scale Step (Note 9) (Note 16) 1kHz Input Signal, First 5 Harmonics 10kHz Input Signal, First 5 Harmonics 1kHz Input Signal 10kHz Input Signal (Note 15)
THD
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco Internal Reference Source Current External Reference Voltage for Specified Linearity External Reference Current Drain CAP Output Voltage (Notes 9, 10) Ext. Reference = 2.5V (Note 9) IOUT = 0 CONDITIONS IOUT = 0 IOUT = 0
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
MIN
q
U
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WU
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MIN
LTC1606/LTC1606A TYP MAX 10 10 10
UNITS V pF k
(Notes 5, 14)
CONDITIONS MIN 83 LTC1606 TYP MAX 90 90 30 - 102 - 94 - 102 - 94 275 40 1 150 150 MIN 87 LTC1606A TYP MAX 90 90 30 - 102 - 94 - 102 - 94 275 40 1 UNITS dB dB dB dB dB dB dB kHz ns s ns
- 87
- 89
Sufficient to Meet AC Specs Sufficient to Meet AC Specs
U
LTC1606/LTC1606A TYP MAX 2.500 5 1 2.520
UNITS V ppm/C A
2.470
2.30
q
2.50 4.096
2.70 100
V A V
3
LTC1606 DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage D15 to D0 Hi-Z Output Capacitance D15 to D0 Output Source Current Output Sink Current VDD = 4.75V VDD = 4.75V VOUT = 0V to VDD, CS High CS High (Note 9) VOUT = 0V VOUT = VDD IO = -10A IO = - 200A IO = 160A IO = 1.6mA
q q q q
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD
q q q
TIMING CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Convert Pulse Width Data Valid Delay After R/C BUSY Delay from R/C BUSY Low BUSY Delay After End of Conversion Aperture Delay Bus Relinquish Time BUSY Delay After Data Valid Previous Data Valid After R/C R/C to CS Setup Time Time Between Conversions Bus Access Byte Delay
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS
q q q
4
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MIN 2.4
LTC1606/LTC1606A TYP MAX 0.8 10 5 4.5
UNITS V V A pF V V V
4.0 0.05 0.10 0.4 10 15 -10 10
V A pF mA mA
UW
MIN 250
LTC1606/LTC1606A TYP MAX 2.5 1.5
UNITS kHz s s ns s ns s ns ns
(Note 11) (Note 9) CL = 30pF
q q q q
40 2.5 65 2.5 100 40
q q
15 20 5 4 15 15 90 2
50
ns ns s ns s
(Notes 9, 10) CL = 30pF CL = 30pF (Notes 9, 10)
q q q q
60 60
ns ns
LTC1606
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
SYMBOL VDD IDD PDIS PARAMETER Positive Supply Voltage Positive Supply Current Power Dissipation CONDITIONS (Notes 9, 10)
q q
POWER REQUIREMENTS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, AGND1 and AGND2 wired together (unless otherwise noted). Note 3: When these pin voltages are taken below ground or above VANA = VDIG = VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below ground or above VDD without latch-up. Note 4: When these pin voltages are taken below ground, they will be clamped by internal diodes. This product can handle input currents of 90mA below ground without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 250kHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a VIN input with respect to ground. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from - 0.5 LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111.
UW
MIN 4.75
LTC1606/LTC1606A TYP MAX 5.25 15 75 20 100
UNITS V mA mW
Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: With CS low the falling R/C edge starts a conversion. If R/C returns high at a critical point during the conversion, it can create errors. For best results, ensure that R/C returns high within 1s after the start of the conversion. Note 12: As measured with fixed resistors shown in Figure 4. Adjustable to zero with external potentiometer. Note 13: Full-scale error is the worst-case of -FS or +FS untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. Note 14: All specifications in dB are referred to a full-scale 10V input. Note 15: Full-power bandwidth is defined as full-scale input frequency at which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of accuracy. Note 16: Recovers to specified performance after (2 * FS) input overvoltage.
5
LTC1606 TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
16.5 16.0 fSAMPLE = 250kHz 16.0
CHANGE IN CAP VOLTAGE (V)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
15.5 15.0 14.5 14.0 13.5 4.5 4.75 5.0 5.25 SUPPLY VOLTAGE (V) 5.5
1606 G01
Typical INL Curve
2.0 1.5 1.0
DNL (LSB)
1.0 0.5 0 -0.5 -1.0 -1.5 0 16384 32768 CODE
1606 G04
POWER SUPPLY REJECTION (dB)
INL (LSB)
0.5 0 -0.5 -1.0 -1.5 -2.0 49152 65535
Nonaveraged 4096 Point FFT Plot
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
90
fSAMPLE = 250kHz fIN = 1.04kHz SINAD = 90dB THD = -100dB
SINAD (dB)
MAGNITUDE (dB)
75 70 65 60
THD (dB)
0
25
75 50 FREQUENCY (kHz)
6
UW
100
1606 G07
Supply Current vs Temperature
fSAMPLE = 250kHz
Change in CAP Voltage vs Load Current
0.10 0.08
15.5
0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08
15.0
14.5
14.0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
1606 G02
-0.10 -15 -13 -11 -9 -7 -5 -3 -1 1 LOAD CURRENT (mA)
3
5
1606 G03
Typical DNL Curve
2.0 1.5 0 -10 -20 -30 -40 -50 -60 -70 0 16384 32768 CODE
1606 G04
Power Supply Rejection vs Ripple Frequency
fSAMPLE = 250kHz
-2.0
49152
65535
1
10
100 1k 10k 100k RIPPLE FREQUENCY (Hz)
1M
LT1606 G06
SINAD vs Input Frequency
fSAMPLE = 250kHz -60
Total Harmonic Distortion (THD) vs Input Frequency
fSAMPLE = 250kHz
85 80
-70
-80
-90
-100
-110 1 10 100 FREQUENCY (kHz) 1000
1606 G08
125
1
10
100
1000
1606 G09
FREQUENCY (kHz)
LTC1606
PI FU CTIO S
VIN (Pin 1): Analog Input. Connect through a 200 resistor to the analog input. Full-scale input range is 10V. AGND1 (Pin 2): Analog Ground. Tie to analog ground plane. REF (Pin 3): 2.5V Reference Output. Bypass with 2.2F tantalum capacitor. Can be driven with an external reference. CAP (Pin 4): Reference Buffer Output. Bypass with 10F tantalum capacitor. The capacitor output voltage is 4.096V when REF = 2.5V. AGND2 (Pin 5): Analog Ground. Tie to analog ground plane. D15 to D8 (Pins 6 to 13): Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low. DGND (Pin 14): Digital Ground. D7 to D0 (Pins 15 to 22): Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low. BYTE (Pin 23): Byte Select. With BYTE low, data will be output with Pin 6 (D15) being the MSB and Pin 22 (D0) being the LSB. With BYTE high, the upper eight bits and the lower eight bits will be switched. The MSB is output on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on Pin 6 and the LSB is output on Pin 13. R/C (Pin 24): Read/Convert Input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the hold state and starts a conversion. With CS low, a rising edge on R/C enables the output data bits. CS (Pin 25): Chip Select. Internally OR'd with R/C. With R/C low, a falling edge on CS will initiate a conversion. With R/C high, a falling edge on CS will enable the output data. BUSY (Pin 26): Output Shows Converter Status. It is low when a conversion is in progress. Data valid on the rising edge of BUSY. CS or R/C must be high when BUSY rises or another conversion will start without time for signal acquisition. VANA (Pin 27): 5V Analog Supply. Bypass to ground with a 0.1F ceramic and a 10F tantalum capacitor. VDIG (Pin 28): 5V Digital Supply. Connect directly to Pin 27.
FU CTIO AL BLOCK DIAGRA
7.35k VIN 9k 2.5k
4k REF 2.5V REF
REF BUF 1.64x
CAP (4.096V) AGND1 AGND2 DGND INTERNAL CLOCK
W
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CSAMPLE
CSAMPLE ZEROING SWITCHES
VANA VDIG
+
16-BIT CAPACITIVE DAC COMP
-
16 OUTPUT LATCHES
SUCCESSIVE APPROXIMATION REGISTER
* * *
D15 D0
CONTROL LOGIC
1606 BD
CS
R/C
BYTE
BUSY
7
LTC1606
TEST CIRCUITS
Load Circuit for Access Timing
5V 1k DBN 1k 30pF DBN 30pF
1606 TC01
Load Circuit for Output Float Delay
5V 1k DBN 1k 30pF DBN 30pF
1606 TC02
A. Hi-Z TO VOH AND VOL TO VOH
B. Hi-Z TO VOL AND VOH TO VOL
A. VOH TO Hi-Z
B. VOL TO Hi-Z
APPLICATIO S I FOR ATIO
Conversion Details
The LTC1606 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 16-bit or two byte parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and R/C inputs. At the start of conversion, the successive approximation register (SAR) is reset. Once a conversion cycle has begun, it cannot be restarted. During the conversion, the internal 16-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, VIN is connected through the resistor divider to
SAMPLE CSAMPLE SI
RIN1 VIN RIN2
SAMPLE HOLD
- +
COMPARATOR DAC VDAC S A R
CDAC
Figure 1. LTC1606 Simplified Equivalent Circuit
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the sample-and-hold capacitor during the acquire phase and the comparator offset is nulled by the autozero switches. In this acquire phase, a minimum delay of 1.5s will provide enough time for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the autozero switches open, putting the comparator into the compare mode. The input switch switches CSAMPLE to ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the VIN input charge. The SAR contents (a 16-bit data word) that represents the VIN are loaded into the 16-bit output latches. Driving the Analog Inputs The nominal input range for the LTC1606 is 10V or (4 * VREF) and the input is overvoltage protected to 25V. The input impedance is typically 10k, therefore, it should be driven with a low impedance source. Wideband noise coupling into the input can be minimized by placing a 1000pF capacitor at the input as shown in Figure 2. An NPO-type capacitor gives the lowest distortion. Place the
AIN 200 VIN 1000pF
16-BIT LATCH
1606 * F01
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33.2k
LTC1606 CAP
1606 * F02
Figure 2. Analog Input Filtering
LTC1606
APPLICATIO S I FOR ATIO
capacitor as close to the device input pin as possible. If an amplifier is to be used to drive the input, care should be taken to select an amplifier with adequate accuracy, linearity and noise for the application. The following list is a summary of the op amps that are suitable for driving the LTC1606. More detailed information is available in the Linear Technology data books and LinearViewTM CD-ROM. LT1007: Low noise precision amplifier. 2.7mA supply current 5V to 15V supplies. Gain bandwidth product 8MHz. DC applications. LT1097: Low cost, low power precision amplifier. 300A supply current. 5V to 15V supplies. Gain bandwidth product 0.7MHz. DC applications. LT1227: 140MHz video current feedback amplifier. 10mA supply current. 5V to 15V supplies. Low noise and low distortion. LT1360: 37MHz voltage feedback amplifier. 3.8mA supply current. 5V to 15V supplies. Good AC/DC specs. LT1363: 50MHz voltage feedback amplifier. 6.3mA supply current. Good AC/DC specs. LT1364/LT1365: Dual and quad 50MHz voltage feedback amplifiers. 6.3mA supply current per amplifier. Good AC/ DC specs. LT1468: 90MHz 22V/s 16-bit accurate amplifier. LT1469: Dual LT1468 Internal Voltage Reference The LTC1606 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.50V. The full-scale range of the ADC is equal to (4 * VREF) or nominally 10V. The output of the reference is connected to the input of a buffer (1.64x) through a 4k resistor (see Figure 3). The input to the buffer or the output of the reference is available at REF (Pin 3). The internal reference can be overdriven with an external reference if more accuracy is needed. The buffer output drives the internal DAC and is available at CAP (Pin 4). The CAP pin can be used to drive a steady DC load of less than 2mA. Driving an AC load is not recommended because it can cause the performance of the converter to degrade.
LinearView is a trademark of Linear Technology Corporation
33.2k 1% 4.096V
+
10F 5
Figure 4. 10V Input Without Trim
+
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REF (2.5V) 2.2F 3 4k BANDGAP REFERENCE
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+
-
0.64R
R
CAP (4.096V) 10F
4 INTERNAL CAPACITOR DAC
1606 * F03
Figure 3. Internal or External Reference Source
For minimum code transition noise, the REF pin and the CAP pin should each be decoupled with a capacitor to filter wideband noise from the reference and the buffer (2.2F tantalum for the REF pin and 10F tantalum for the CAP pin). To prevent the 10F bypass capacitor from discharging through the CAP pin if the positive supply (VDIG and VANA) were to drop, a diode (1N4148 or equivalent) can be placed between the CAP pin and the positive supply. Offset and Gain Adjustments The LTC1606 offset and full-scale errors have been trimmed at the factory with the external resistors shown in Figure 4. This allows for external adjustment of offset and full scale in applications where absolute accuracy is important. See Figure 5 for the offset and gain trim circuit. First, adjust the offset to zero by adjusting resistor R3. Apply an input voltage of -152.6V (- 0.5LSB) and adjust R3 so the
1 200 1% 2 2.2F 3 4
10V INPUT
VIN AGND1 LTC1606 REF CAP AGND2
1606 * F04
9
LTC1606
APPLICATIO S I FOR ATIO
code is changing between 1111 1111 1111 1111 and 0000 0000 0000 0000. The gain error is trimmed by adjusting resistor R4. An input voltage of 9.999542V (+FS - 1.5LSB) is applied to VIN and R4 is adjusted until the output code is changing between 0111 1111 1111 1110 and 0111 1111 1111 1111. Figure 6 shows the bipolar transfer characteristic of the LTC1606.
1 200 1% 2.2F 33.2k 1% 5V 576k R4 50k R3 50k 2
10V INPUT
VIN AGND1
3
REF LTC1606
+
10F
4 5
CAP
AGND2
1606 * F05
Figure 5. 10V Input with Offset and Gain Trim
011...111 011...110 BIPOLAR ZERO 2000
OUTPUT CODE
000...001 000...000 111...111 111...110
COUNTS
FS = 20V 1LSB = FS/65536
100...001 100...000 -FS/2
-1 0V 1 LSB LSB INPUT VOLTAGE (V)
FS/2 - 1LSB
1606 * F06
Figure 6. LTC1606 Bipolar Transfer Characteristics Table 1
ERROR TERM Offset Error + Full-Scale Error - Full-Scale Error WITH BOTH EXTERNAL RESISTORS INCLUDED - 10mV < Error < 10mV - 0.25% < Error < 0.25% - 0.50% < Error < 0.50% - 0.25% < Error < 0.25% - 0.50% < Error < 0.50%
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If the external resistors are not used, the resulting offset and gain error ranges are shown in Table 1. DC Performance One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC signal is applied to the input of the ADC and the resulting output codes are collected over a large number of conversions. For example in Figure 7, the distribution of output code is shown for a DC input that has been digitized 4096 times. The distribution is Gaussian and the RMS code transition is about 0.65LSB. DIGITAL INTERFACE Internal Clock The ADC has an internal clock that is trimmed to achieve a typical conversion time of 2.3s. No external adjustments are required and, with the typical acquisition time of 1s, throughput performance of 250ksps is assured.
2500 1500 1000 500 0 -3 -2 -1 0 CODE 1 2 3 4
1606 * F07
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+
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Figure 7. Histogram for 4096 Conversions
WITHOUT THE EXTERNAL 33.2k RESISTOR 10mV < Error< 55mV - 1.3% < Error < -0.10% 0.25% < Error < 1.40%
WITHOUT EITHER EXTERNAL RESISTOR INCLUDED 54mV < Error < 155mV - 3.40% < Error < -0.85% 2.10% < Error < 6.15%
LTC1606
APPLICATIO S I FOR ATIO
Timing and Control
Conversion start and data read are controlled by two digital inputs: CS and R/C. To start a conversion and put the sample-and-hold into the hold mode, bring CS and R/C low for no less than 40ns. Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output and this is low while the conversion is in progress. There are two modes of operation. The first mode is shown in Figure 8. The digital input R/C is used to control the start of conversion. CS is tied low. When R/C goes low, the sample-and-hold goes into the hold mode and a conversion is started. BUSY goes low and stays low during the conversion and will go back high after the conversion has been completed and the internal output shift registers have been updated. R/C should remain low for no less than 40ns. During the time R/C is low, the digital outputs are in a Hi-Z state. R/C should be brought back high within 1s after the start of the conversion to ensure that no errors occur in the digitized result. The second mode, shown in
t1 R/C t 11 t2 BUSY t6 MODE ACQUIRE CONVERT t CONV t9 DATA MODE PREVIOUS DATA VALID t7 Hi-Z PREVIOUS DATA VALID NOT VALID t8 DATA VALID Hi-Z DATA VALID
1606 * F08
t3
Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low)
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Figure 9, uses the CS signal to control the start of a conversion and the reading of the digital output. In this mode the R/C input signal should be brought low no less than 10ns before the falling edge of CS. The minimum pulse width for CS is 40ns. When CS falls, BUSY goes low and will stay low until the end of the conversion. BUSY will go high after the conversion has been completed. The new data is valid when CS is brought back low again to initiate a read. Again, it is recommended that both R/C and CS return high within 1s after the start of the conversion. Output Data The output data can be read as a 16-bit word or it can be read as two 8-bit bytes. The format of the output data is two's complement. The digital input pin BYTE is used to control the two byte read. With the BYTE pin low, the first eight MSBs are output on the D15 to D8 pins and the eight LSBs are output on the D7 to D0 pins. When the BYTE pin is taken high, the eight LSBs replace the eight MSBs (Figure 10).
t4 t5 ACQUIRE t ACQ CONVERT
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LTC1606
t 10 R/C
t 10
t 10
t 10
t1 CS
t1
t3 BUSY t6 MODE ACQUIRE CONVERT t CONV HI-Z
t4
ACQUIRE
DATA BUS
DATA VALID t 12 t7
Hi-Z
1606 * F09
Figure 9. Using CS to Control Conversion and Read Timing
t 10 R/C
t 10
CS
BYTE
PINS 6 TO 13
Hi-Z
HIGH BYTE t 12 t 12 LOW BYTE
LOW BYTE t7 HIGH BYTE
Hi-Z
PINS 15 TO 22
Hi-Z
Hi-Z
1606 * F10
Figure 10. Using CS and BYTE to Control Data Bus Read Timing
12
LTC1606
APPLICATIO S I FOR ATIO
Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Signal-to-Noise Ratio The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. A typical LTC1606 has a SINAD of 90dB and THD of -100dB with a 250kHz sampling rate and a 1kHz input. Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:
V + V3 + V4 ... + VN THD = 20 log 2 V1
2
2
2
2
U
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. Board Layout, Power Supplies and Decoupling Wire wrap boards and molded sockets are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1606, a printed circuit board is required. Layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND. Pay particular attention to the design of the analog and digital ground planes. The DGND pin of the LTC1606 should be tied to the analog ground plane. Placing the bypass capacitor as close as possible to the power supply, the reference and reference buffer output is very important. Low impedance common returns for these bypass capacitors are essential to low noise operation of the ADC, and the foil width for these tracks should be as wide as possible. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible.
W
UU
13
LTC1606
PACKAGE DESCRIPTIO U
Dimensions in inches (millimeters) unless otherwise noted.
G Package 28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
10.07 - 10.33* (0.397 - 0.407) 28 27 26 25 24 23 22 21 20 19 18 17 16 15
7.65 - 7.90 (0.301 - 0.311)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 5.20 - 5.38** (0.205 - 0.212) 1.73 - 1.99 (0.068 - 0.078)
0 - 8
0.13 - 0.22 (0.005 - 0.009)
0.55 - 0.95 (0.022 - 0.037)
0.65 (0.0256) BSC
NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
0.25 - 0.38 (0.010 - 0.015)
0.05 - 0.21 (0.002 - 0.008)
G28 SSOP 1098
14
LTC1606
PACKAGE DESCRIPTIO
0.291 - 0.299** (7.391 - 7.595) 0.010 - 0.029 x 45 (0.254 - 0.737) 0 - 8 TYP
0.009 - 0.013 (0.229 - 0.330)
NOTE 1 0.016 - 0.050 (0.406 - 1.270)
NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
Dimensions in inches (millimeters) unless otherwise noted.
SW Package 28-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.697 - 0.712* (17.70 - 18.08) 28 27 26 25 24 23 22 21 20 19 18 17 16 15
NOTE 1
0.394 - 0.419 (10.007 - 10.643)
1 0.093 - 0.104 (2.362 - 2.642)
2
3
4
5
6
7
8
9
10
11
12
13
14 0.037 - 0.045 (0.940 - 1.143)
0.050 (1.270) BSC
0.014 - 0.019 (0.356 - 0.482) TYP
0.004 - 0.012 (0.102 - 0.305)
S28 (WIDE) 1098
15
LTC1606
TYPICAL APPLICATIO U
5V
High Impedance Buffered Input Exhibits 100dB SFDR and 98dB THD Performance
+
10F 15V 0.1F LTC1606 VIN 10V RS 20k 3 28 VDIG 27 VANA 6 TO 13 15 TO 22 D15 TO D0 16-BIT OR 2 BYTE PARALLEL BUS 0.1F
+ -
R1 50
7 LT1468
R2 200 6 10V C1 1000pF 4.096V R3 33.2k
1 VIN
7.35k
2
16-BIT SAMPLING ADC 2.5k 9k
4
0.1F
4 CAP 10F 2.5V 1.65x BUFFER 4k REFERENCE AGND1 AGND2 2 5 DGND 14 SINGLE POINT GROUND
1606 TA02
BUSY CONTROL LOGIC AND TIMING CS R/C BYTE
26 25 24 23 DIGITAL CONTROL SIGNALS
-15V
3 REF 2.2F
RELATED PARTS
PART NUMBER LTC1274/LTC1277 LTC1415 LTC1418 LTC1419 LT1460-2.5 LT1461 LTC1594/LTC1598 LTC1604 LTC1605 LTC1605-1/LTC1605-2 LTC1608 DESCRIPTION Low Power 12-Bit, 100ksps ADCs Single 5V, 12-Bit, 1.25Msps ADC 14-Bit, 200ksps ADC Low Power 14-Bit, 800ksps ADC Micropower Precision Series Reference Precision Bandgap Reference Micropower 4-/8-Channel 12-Bit ADCs 16-Bit, 333ksps ADC 16-Bit, 100kHz ADC 16-Bit, 100kHz ADC 16-Bit, 500ksps ADC COMMENTS 10mW Power Dissipation, Parallel/Byte Interface 55mW Power Dissipation, 72dB SINAD 15mW, Serial or Parallel Interface True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation 0.075% Max, 10ppm/C Max, Only 130A Supply Current 0.04% Max, 3ppm/C Max Serial I/O, 3V and 5V Versions 2.5V Input, 90dB SINAD, 100dB THD, No Missing Codes Pin Compatible with LTC1606 0V to 4V/4V Input Range, Pin Compatible with LTC1606 2.5V Input, No Missing Codes, Pin Compatible with LTC1604
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
1606f LT/LCG 0301 4K * PRINTED IN THE USA
(c) LINEAR TECHNOLOGY CORPORATION 2000

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